1. Field of the Invention
The present invention relates to a method of manufacturing the multi-level metallic interconnect (MLM) of a semiconductor device. More particularly, the present invention relates to a copper damascene manufacturing process.
2. Description of Related Art
To keep up with the manufacturing cost, deep-submicron devices are now being manufactured. A variety of advanced materials are also employed to increase device operation speed and improve device reliability.
In the backend production of semiconductor devices, current density loading of metal lines is greatly increased due to the large reduction in metal line width. Since aluminum provides little resistance against electromigration, conventional aluminum metal lines are increasingly affected by electromigration problems. Consequently, device reliability will deteriorate if the use of aluminum lines is continued.
To resolve the problems resulting from fabricating deep submicron devices, choosing a metal with a small electromigration such as copper is important. However, copper is a metal that resists the etching action of most conventional gaseous etchants so that copper lines and copper plugs simply cannot be fabricated by a conventional method. Hence, a damascene process must be used instead.
FIGS. 1A through 1F are schematic cross-sectional views showing the progression of steps in a conventional copper damascene process for producing a copper line and a copper plug.
As shown in FIG. 1A, a silicon oxide layer 102 is formed over a substrate 100. A silicon nitride layer 104 is formed over the silicon oxide layer 102, and then another silicon oxide layer 106 is formed over the silicon nitride layer 104. The silicon oxide layer 102, the silicon nitride layer 104 and the silicon oxide layer 106 can be formed by plasma-enhanced chemical vapor deposition (PECVD), and the layers together serve as an inter-metal dielectric (IMD) layer.
As shown in FIG. 1B, photolithographic and etching techniques are used to form a trench line 108 in the silicon oxide layer 106. The silicon nitride layer 104 serves as an etching stop layer when the trench line 108 is formed so that over-etching is prevented.
As shown in FIG. 1C, again using photolithographic and etching techniques, the silicon nitride layer 104 and the silicon oxide layer 102 at the bottom of the trench line 108 are etched to form a via 110.
As shown in FIG. 1D, a metal barrier layer 112 and a copper layer 114 are sequentially formed conformal to the profile of the trench line 108, the via 110 and the silicon oxide layer 106. The metal barrier layer 112 and the copper layer 114 can be formed, for example, by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
As shown in FIG. 1E, using the copper layer 114 as a seeding layer, copper electroplating is carried out to form a second copper layer 116 over the copper layer 114.
As shown in FIG. 1F, a portion of the metal barrier layer 112, the copper layers 114 and 116 are removed. Ultimately, only a metal barrier layer 112a, copper layers 114a and 116a are retained inside the trench line 108 and the via 110. The metal barrier layer 112, the copper layers 114 and 116 above the silicon oxide layer 106 can be removed by chemical-mechanical polishing (CMP).
As the dimensions of a device shrink, forming a conformal metal barrier layer and a conformal copper seeding layer inside the trench line 108 and the via 110 is becoming harder. This is because of the difficulty in depositing a uniform layer inside an opening having a high aspect ratio (HAR). In addition, forming a copper plug in an opening with a high aspect ratio is likely to result in the formation of a void or a seam in the center of the plug. To form a seeding layer of copper, special copper machines for physical or chemical vapor deposition has to be used. Ultimately, production cost is likely to increase.